The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device using address transition detection for controlling the power consumption of the memory device.
In the semiconductor memory devices, reduction of electric power consumption is an important target. Thus, static random access memories (SRAMs) as well as dynamic random access memories (DRAMs) use address transition detection (ATD) technology such that peripheral circuits in the chip, such as sense amplifiers, word drivers, and the like, are activated only when a transition has occurred in the address signal. By employing such an ATD technology, one can deactivate many peripheral circuits when no transition occurs in the address signal.
FIG. 1 shows a conventional SRAM that uses such an ATD circuit.
Referring to FIG. 1, the SRAM has a chip 1 in which a memory cell array 2 is provided, wherein the memory cell array 2 includes a plurality of memory cells 2a arranged in rows and columns. As usual, the memory cells 2a are selected by selecting a corresponding word line WL and a bit line BL.
In addition to the memory cell array 2, the chip 1 includes various peripheral circuits, such as an address buffer circuit 3 for receiving address signals A.sub.IN1 -A.sub.IN8 supplied externally, a word line driver 4 for decoding row address signals included in the address signals A.sub.IN1 -A.sub.IN8 and for selecting a word line WL specified by the row address signals, and a column switch circuit 5 for decoding column address signals included in the address signals A.sub.IN1 -A.sub.IN8 and for selecting a bit line BL specified by the column address signals.
Further, the chip 1 includes a sense amplifier 6 for amplifying the data read out from the selected memory cell 2a in the memory cell array 2 via the column switch 5 and an output buffer circuit 7 for producing output data D.sub.OUT by latching the output of the sense amplifier 6.
In addition, there is provided an ATD circuit 8 in the chip 1 for detecting the transition of the address signals A.sub.IN1 -A.sub.IN8, wherein the ATD circuit 8 controls the activation of the word driver 4 and the sense amplifier 6 based upon the detection of transition in the address signals A.sub.IN1 -A.sub.IN8. More specifically, the ATD circuit 8 of the SRAM of FIG. 5 produces an output signal ATD.sub.OUT such that the word driver 4 and the sense amplifier 5 are deactivated as long as the output signal ATD.sub.OUT is stationary and activated only when the output signal ATD.sub.OUT has caused transition.
FIG. 2 shows the construction of the ATD circuit 8.
Referring to FIG. 2, the reference numerals 9-16 designate address input terminals supplied with the address signals A.sub.IN1 -A.sub.IN8, and the address signals A.sub.IN1 -A.sub.IN8 thus received are supplied to corresponding detection circuits 17-24 for detection of address transition. It should be noted that each of the detection circuits 17-24 has an identical construction shown in FIG. 6 and includes inverters 25 and 26 connected in series and NAND gates 27-29 forming a flip-flop circuit together with resistors 30 and 31, wherein the output of the inverter 25 is supplied to the NAND gate 38 while the output of the inverter 26 is supplied to the NAND gate 27. Further, capacitors 32 and 33 cooperate with the resistors 30 and 31 in the flip-flop circuit to form a CR circuit. Further, the output of the flip-flop circuit is obtained via a NAND gate 29.
In the illustrated construction of FIG. 2, the output signals of the detection circuits 17-19 are supplied to a NAND gate 34. Similarly, the output signals of the detection circuits 20-22 are supplied to a NAND gate 35, and the output signals of the detection circuits 23 and 24 are supplied to a NAND gate 36. Further, the output signals of the NAND gates 34-36 are supplied to a NOR gate 37 that produces the aforementioned ATD output signal ATD.sub.OUT. As already noted, the output signal ATD.sub.OUT controls the word driver 4 and the sense amplifier 6. It should be noted that the NAND gates 34-36 and a NOR gate 37 form an OR gate as a whole.
FIGS. 3A-3J are diagrams showing the waveform for explaining the operation of the SRAM of FIG. 1.
Referring to the drawings, FIG. 3A shows the waveform of the address signal A.sub.IN1 supplied to the input terminal 9 while FIG. 3B shows the waveform of the output signal of the inverter 25 at a node N.sub.1. Further, FIG. 3C shows the waveform of the output signal of the inverter 26 at a node N.sub.2.
FIG. 3D, on the other hand, shows the waveform of the output signal of the NAND circuit 28 obtained at a node N.sub.4 while FIG. 3E shows the voltage level of a node N.sub.5 at which the resistor 30 and the capacitor 32 are connected. Similarly, FIG. 3F shows the waveform of the output signal of the NAND circuit obtained at a node N.sub.3 while FIG. 3G shows the voltage level of a node N.sub.6 at which the resistor 31 and the capacitor 33 are connected.
FIG. 3H, on the other hand, shows the waveform of the output signal of the detection circuit 17, FIG. 3I shows the waveform of the output signal ATD.sub.OUT obtained at the ATD circuit 8, and FIG. 3J shows the waveform of the output signal D.sub.OUT produced by the output buffer circuit 7. It should be noted that the nodes N.sub.1 -N.sub.6 are shown in the circuit diagram of FIG. 2.
Thus, in the case that the address signal A.sub.IN1 is stabilized at a low level state, it will be noted that the node N.sub.1 assumes a high level state, the node N.sub.2 assumes a low level state, the node N.sub.3 and the node N.sub.6 assume a high level state, the node N.sub.4 and the node N.sub.5 assume a low level state, and the node N.sub.7 assumes a high level state.
In the case that the address signal A.sub.IN1 has caused a transition to a high level state and stabilized at such a high level state, on the other hand, the node N.sub.1 assumes a low level state, the node N.sub.2 assumes a high level state, the node N.sub.4 and the node N.sub.5 assume a high level state, and the node N.sub.3 and the node N.sub.6 assume a low level state. Further, the node N.sub.7 assumes a high level state. It should be noted that the high level state of the node N.sub.7 occurs similarly to the case when the address signal A.sub.IN1 is stabilized at the low level state.
Thus, as long as there occurs no transition in the address signals A.sub.IN1 -A.sub.IN8, it should be noted that the transition detection circuits 17-24 produce high level output signals and the NAND circuits 34-36 produce low level output signals in response thereto. Thereby, the ATD output signal ATD.sub.OUT is held at the high level state, and both of the word drivers 4 and the sense amplifiers 6 are the deactivated. In other words, no reading of data is made from the memory cell.
When the address signal A.sub.IN1 goes high as indicated in FIG. 3A, on the other hand, the node N.sub.1 goes low, the node N.sub.2 goes high, and the node N.sub.4 goes high. As a result, the level of the node N.sub.5 increases gradually from the low level state to the high level state in accordance with the time constant of the CR circuit in the flip-flop circuit. Further, the node N.sub.7 goes low. When the node N.sub.7 goes low, the output signal of the NAND circuit 34 goes high and the ATD output signal ATD.sub.OUT goes low. Thus, the word driver 4 and the sense amplifier 6 are both activated in response to the low level state of the ATD output signal ATD.sub.OUT, and reading of data is made from the selected memory cell 2a in the memory cell array 2. The data thus read out from the selected memory cell 2a is then latched at the output buffer circuit 7 as the output data of the memory device.
When the voltage at the node N.sub.5 reaches a threshold voltage VT.sub.H of the NAND circuit 27, the node N.sub.3 goes low and the level of the node N.sub.6 decreases gradually from the high level state to the low level state. Further, the node N.sub.7 goes high and the ATD output signal ATD.sub.OUT goes high. As a result, the word driver 4 and the sense amplifier 6 are deactivated again in response to the crossing of the level of the node N.sub.5 across the threshold V.sub.TH. On the other hand, the output buffer circuit 7 continues outputting the output data D.sub.OUT already latched therein.
Thus, it will be noted that the SRAM of FIG. 1 activates the word driver 4 and the sense amplifier 6 only for a limited duration when the address signals A.sub.IN1 -A.sub.IN8 have caused a transition, by setting the level of the ATD output signal ATD.sub.OUT to the low level state. Only in such a limited duration, the data is read from the memory cell and latched in the output buffer circuit 7. After this, the ATD output signal ATD.sub.OUT returns to the high level state and the word driver 4 and the sense amplifier 6 are again deactivated. It should be noted that the time constant of the RC circuit formed by the resistor 30 and the capacitor 32 or by the resistor 31 and the capacitor 33, is set sufficiently large for a stabilized operation of the sense amplifier 6. In other words, the duration in which the word decoder 4 and the sense amplifier 6 are activated is sufficiently long for reading the content of the memory cell with reliability. Thus, the SRAM having the ATD circuit 8 can effectively reduce the power consumption of the semiconductor memory device by limiting the duration in which the word driver 4 and the sense amplifier 6 are activated.
In such a conventional semiconductor memory device that uses ATD technology, it should be noted that there can be a case in which erroneous data is latched in the output buffer circuit 7 when a noise or glitch is superposed to the address signals A.sub.IN1 -A.sub.IN8. Once such erroneous output data is read out, the data is held continuously in the output buffer circuit 7 until the next reading is made. Such erroneous data may lead the system that uses the semiconductor memory device to a failure.
FIGS. 4A-4J explain such an erroneous reading of data caused by the noise in the address signal. It should be noted that FIGS. 8A-8J correspond to FIGS. 3A-3J. Thus, no description will be given to each of the waveform appearing in FIGS. 8A-8J.
Thus, when a glitch is superposed on the address signal A.sub.IN1 as indicated in FIG. 4A and the signal A.sub.IN1 goes high momentarily, the node N.sub.1 goes low as indicated in FIG. 4B, the node N.sub.2 goes high as indicated in FIG. 4C, and the node N.sub.4 goes high as indicated in FIG. 4D. As a result, the level of the node N.sub.5 starts to rise from the low level state as indicated in FIG. 4E. Further, the node N.sub.7 goes low as indicated in FIG. 4H in response to the transition at the node N.sub.4. In response to the transition in the node N.sub.7, the ATD output signal ATD.sub.OUT goes low as indicated in FIG. 4I. In other words, there occurs an activation of the word decoder 4 and the sense amplifier 6 in response to the noise superposed to the address signal A.sub.IN1.
It should be noted that the address signal A.sub.IN1 returns immediately to the low level state after the foregoing momentary transition to the high level state when such a transition is caused by a noise impulse or glitch. As a result, the node N.sub.1 returns immediately to the high level state. Similarly, the node N.sub.2 returns to the low level state and the node N.sub.4 returns to the low level state. Thus, the level of the node N.sub.5 never reaches the threshold voltage V.sub.H of the NAND circuit 27 but returns again to the low level state as indicated in FIG. 4E. Thus, the node N.sub.3 and hence the node N.sub.6 maintain the high level state as indicated in FIGS. 4F and 4G. As the node N.sub.4 returns immediately to the low level state in the present situation while the node N.sub.3 being held at the high level state, the node N.sub.7 immediately returns to the high level state in response to the trailing edge of the voltage signal at the node N.sub.4 and the ATD output signal ATD.sub.OUT also returns immediately to the high level.
Thus, when such a momentary transition occurs in the address signal A.sub.IN1, the word decoder 4 and the sense amplifier 6 are activated erroneously, while the duration in which the word decoder 4 and the sense amplifier 6 are activated is very short, too short for stabilizing the operation of the word decoder 4 or the sense amplifier 6. Thus, the output buffer circuit 7 holds the erroneous output of the sense amplifier indicative of the memory cell 2a selected erroneously by the word decoder 4. When a system cooperating with the SRAM uses the data that is latched in the output buffer circuit 7, therefore, there is a substantial risk that the system hangs or functions erroneously.